1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device preferably applied to a FBGA (Fine pitch Ball Grid Array) type DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
There is known a conventional semiconductor device disclosed in Japanese Patent Laid-Open No. 2001-185576 (Patent Document 1). The semiconductor device disclosed in Patent Document 1 is provided with pads for signal lines (signal pads), pads for a power supply potential (power supply pads), and pads for a ground potential (ground pads). In this semiconductor device, in order to reduce a power supply based inductance in the semiconductor device, all of the pads are formed on a surface of a wiring board, the surface connected with a semiconductor pellet (semiconductor chip) by wire bonding, and are connected with a signal contact, a power supply potential contact, and a ground potential contact formed on another surface of the wiring board electrically independently one another by through hole conductors. The power supply pads and the ground pads are respectively arranged at the both sides of the signal pads.
However, although Patent Document 1 discloses an effective technique for reducing the power supply based inductance in the semiconductor device, Patent Document 1 does not disclose a reduction in size (size shrink) of a semiconductor chip used in the semiconductor device.
In the semiconductor device such as a DRAM, a reduction in size of a semiconductor chip is desired. By the reduction in size of the semiconductor chip, a number of semiconductor chips obtained from a piece of silicon wafer can be increased, and final costs of the semiconductor device can be reduced.
For that reason, semiconductor manufactures try to reduce sizes of components such as a transistor and a capacitor in the semiconductor device and to reduce sizes of wires in the chip by improvement of the production process. With these efforts, chips in DRAMs having the same capacity have been remarkably made small.
With techniques similar to the wiring in the chip and the production process for the semiconductor chip, pads for transmitting and receiving signals between a semiconductor chip and a package, a board, or a memory module and for supplying a power supply potential and a ground potential to the chip can be made small principally in the same way.
However, these pads are required to be capable of transmitting and receiving signals to/from the outside of the chip, such as a package. Therefore, pads are required to have sizes so as to be used in a step called “post-process”, for example, packaging. In a FBGA using a wiring board, it is necessary to connect pads and wires inside the package reliably by wire bonding. Also, in a FBGA using a tape substrate, it is necessary to connect pads and wires inside the package reliably by a flexible tape substrate. The connection technique in the post-process has not advanced rapidly as compared with the processing technique inside the chip. Therefore, even if the size inside the chip is significantly reduced, there is a possibility in that connection is performed by only current pad sizes and current pad pitches under constraints on the connection means for the semiconductor chip and the package. Pads for semiconductor chips in the current semiconductor producing technique are formed in a square or a rectangle having a side of approximate 80 to 100 μm, and pad pitches are larger than the side.
As described in Patent Document 1, it is preferable that the power supply pads and the ground pads are arranged at both sides of the signal pads on the main surface of the semiconductor chip in view of electrical characteristics. However, this causes an increase of pads to provide a problem of preventing a reduction in size of the semiconductor chip. On the other hand, when attentions are paid to only size reduction of the semiconductor chip and then the number of power supply pads and ground pads is reduced excessively, it is impossible to make electrical characteristics, namely, inductance of power supply and ground wires small sufficiently, and, as a consequence, there is a problem in that the semiconductor device cannot be operated at high speed.
This situation causes a problem in that a further reduction in size of chip cannot be attained under constraints on pads to be arranged on the main surface of the chip regardless of the situation in that a reduction in size of the semiconductor chip can be attained by improvement of the production process for the semiconductor chip.